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january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 1/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary product list SM79108L25, 25 mhz 8kb internal memory mcu sm79108c40, 40 mhz 8kb internal memory mcu description the sm79108 series product is an 8 - bit single chip micro controller with 8 kb flash & 256 bytes ram embedded. it has 4-channel, 8-bit adc function build-in, 1-channel spwm and 1-channel pwm build-in and a14(segment) x 4(common) lcd driver. it provides hardware features and a powerful instruction set necessary to make it a versatile and cost effective controller for those applications demand up to 32 i/o pins for pdip package or up to 36 i/o pins for plcc/qfp package, or applications which need up to 64k byte flash memory for program and/or for data. to program the flash block, a commercial programmer is capable to do it. ordering information yywwv: production date code identifier sm79108ihhk yy: year, ww: weak, v: version i: process identifier {l=3.0v ~ 3.6v, c=4.5v ~ 5.5v} hh: working clock in mhz {25, 40} k: package type postfix {as below table} features working voltage: 3.0v ~ 3.6v for l version 4.5v ~ 5.5v for c version general 8052 family compatible 12 clocks per machine cycle 8 kb internal flash memory 256 bytes on-chip data ram three 16 bit timers/counters four 8-bit i/o ports for pdip package four 8-bit i/o ports + one 4-bit i/o ports for plcc or qfp package a14 x 4 lcd driver (p0, p2, ale, psen) 1 channel spwm (p1.2) 1 channel pwm (p1.5) full duplex serial channel bit operation instruction industrail level 8-bit unsigned division 8-bit unsigned multiply bcd arithmetic direct addressing indirect addressing nested interrupt two priority level interrupt a serial i/o port power save modes: idle mode and power down mode code protection function one watch dog timer (wdt) low emi (inhibit ale) postfix package pin/pad configuration dimension p 40l pdip page 2 page 22 j 44l plcc page 2 page 23 q 44l qfp page 2 page 24 with 8kb flash & 256 bytes ram embedded 8 - bit micro-controller taiwan 4f, no. 1 creation road 1, science-based industrial park, hsinchu, taiwan 30077 tel: 886-3-578-3344 #2667 886-3-579-2987 fax: 886-3-5792960 886-3-5780493
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 2/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary pin configurations seg10/ad3/p0.3 seg11/ad3/p0.2 seg12/ad3/p0.1 seg13/ad3/p0.0 vdd p4.2 t2/p1.0 t2ex/p1.1 spwm/p1.2 p1.3 p1.4 p2.4/a12/seg0 p2.3/a11/com3 p2.2a10/com2 p2.1/a9/com1 p2.0a8/com0 p4.0 vss xtal1 xtal2 p3.7/#rd/adc3 p3.6/#wr/adc2 p0.4/ad4/seg9 p0.5/ad5/seg8 p0.6/ad6/seg7 p0.7/ad7/seg6 #ea p4.1 ale/seg5 #psen/seg4 p2.7/a15/seg3 p2.6/a14/seg2 p2.5/a13/seg1 pwm/p1.5 p1.6 p1.7 res rxd/p3.0 txd/p3.1 #int0/p3.2 #int1/p3.3 adc0/t0/p3.4 adc1/t1/p3.5 sm79108 jhhq 44l qfp (top view) 33 32 31 30 27 26 25 24 23 29 28 22 21 20 18 17 16 15 14 13 19 12 11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 p4.3 sm79108 ihhp (top view) 40l pdip vdd p0.0/ad0/seg13 p0.1/ad1/seg12 p0.2/ad2/seg11 p0.3/ad3/seg10 p0.4/ad4/seg9 p0.5/ad5/seg8 p0.6/ad6/seg7 p0.7/ad7/seg6 #ea ale/seg5 #psen/seg4 p2.7/a15/seg3 p2.6/a14/seg2 p2.5/a13/seg1 p2.4/a12/seg0 p2.3/a11/com3 p2.2/a10/com2 p2.1/a9/com1 p2.0/a8/com0 t2/p1.0 t2ex/p1.1 spwm/p1.2 p1.3 p1.4 pwm/p1.5 p1.6 p1.7 res rxd/p3.0 txd/p3.1 #int/p3.2 #int1/p3.3 adc0/t0/p3.4 adc1/t1/p3.5 adc2/#wr/p3.6 adc3/#rd/p3.7 xtal1 xtal2 vss 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 10 40 39 38 37 36 35 34 33 32 31 30 28 27 26 25 24 23 22 21 29 p1.4 p1.3 p1.2/spwm p1.1/t2ex p1.0/t2 p4.2 vdd p0.0/ad0/seg13 p0.2/ad2/seg11 p0.3/ad3/seg10 p0.1/ad1/seg12 p0.4/ad4/seg9 p0.5/ad5/seg8 p0.6/ad6/seg7 p0.7/ad7/seg6 #ea p4.1 ale/seg5 #psen/seg4 p2.7/a15/seg3 p2.6/a14/seg2 p2.5/a13/seg1 pwm/p1.5 p1.6 p1.7 res rxd/p3.0 p4.3 txd/p3.1 #int0/p3.2 #int1/p3.3 adc0/t0/p3.4 adc1/t1/p3.5 adc2/#wr/p3.6 adc3/#rd/p3.7 xtal2 xtal1 vss p4.0 com0/a8/p2.0 com1/a9/p2.1 com2/a10/p2.2 com3/a11/p2.3 seg0/a12/p2.4 sm79108 jhhj 44l plcc (top view) 6 5 4 3 2 14443 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 3/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary timer 2 timer 1 timer 0 stack pointer decoder & register 256 bytes ram block diagram reset circuit power circuit interrupt circuit res vdd vss to pertinent blocks to whole chip to pertinent blocks acc buffer2 buffer1 alu psw buffer dptr pc incrementer program counter register 8 k bytes flash memory port 1 latch port 2 latch port 3 latch port 0 driver & mux port 1 driver & mux port 2 driver & mux port 3 driver & mux 8 8 8 8 wdt timing generator xtal2 xtal1 #ea ale/seg5 #psenseg4 to whole system instruction register port 0 latch adc spwm pwm lcd driver (14 x 4)
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 4/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary pin descriptions 40l pdip pin# 44l qfp pin# 44l plcc pin# symbol active i/o (gpio) names 1 40 2 p1.0/t2 i/o bit 0 of port 1 & timer 2 clock out 2 41 3 p1.1/t2ex i/o bit 1 of port 1 & timer 2 control 3 42 4 p1.2/spwm i/o bit 2 of port 1 & spwm channel 4 43 5 p1.3 i/o bit 3 of port 1 5 44 6 p1.4 i/o bit 4 of port 1 6 1 7 p1.5/pwm i/o bit 5 of port 1 & pwm channel 7 2 8 p1.6 i/o bit 6 of port 1 8 3 9 p1.7 i/o bit 7 of port 1 9 4 10 res h i reset 10 5 11 p3.0/rxd i/o bit 0 of port 3 & receive data 11 7 13 p3.1/txd i/o bit 1 of port 3 & transmit data 12 8 14 p3.2/#int0 -/l i/o bit 2 of port 3 & low true interrupt 0 13 9 15 p3.3/#int1 -/l i/o bit 3 of port 3 & low true interrupt 1 14 10 16 p3.4/t0/adc0 i/o bit 4 of port 3 & adc channel 0 & timer 0 15 11 17 p3.5/t1/adc1 i/o bit 5 of port 3 & adc channel 1 &timer 1 16 12 18 p3.6/#wr/adc2 i/o bit 6 of port 3 & adc channel 2 & external memory write 17 13 19 p3.7/#rd/adc3 i/o bit 7 of port 3 & adc channel 3 & external memory read 18 14 20 xtal2 o crystal out 19 15 21 xtal1 i crystal in 20 16 22 vss sink voltage, ground 21 18 24 p2.0/a8/com0 i/o bit 0 of port 2 & bit 8 of external memory address & lccd common 0 output 22 19 25 p2.1/a9/com1 i/o bit 1 of port 2 & bit 9 of external memory address & lccd common 1 output 23 20 26 p2.2/a10/com2 i/o bit 2 of port 2 & bi t 10 of external memory address & lccd common 2 output 24 21 27 p2.3/a11/com3 i/o bit 3 of port 2 & bi t 11 of external memory address & lccd common 3 output 25 22 28 p2.4/a12/seg0 i/o bit 4 of port 2 & bit 12 of external memory address & lccd seg 0 output 26 23 29 p2.5/seg1 i/o bit 5 of port 2 & lccd seg 1 output 27 24 30 p2.6/seg2 i/o bit 6 of port 2 & lccd seg 2 output 28 25 31 p2.7/seg3 i/o bit 7 of port 2 & lccd seg 3 output 29 26 32 #psen/seg4 o program storage enable & lccd seg 4 output 30 27 33 ale/seg5 o address latch enable & lccd seg 5 output 31 29 35 #ea l i external access 32 30 36 p0.7/ad7/seg6 i/o bit 7 of port 0 & dat a/address bit 7 of external memory & lccd seg 6 output 33 31 37 p0.6/ad6/seg7 i/o bit 6 of port 0 & data/ address bit 6 of external memory & lccd seg7 output 34 32 38 p0.5/ad5/seg8 i/o bit 5 of port 0 & dat a/address bit 5 of external memory & lccd seg 8 output 35 33 39 p0.4/ad4/seg9 i/o bit 4 of port 0 & dat a/address bit 4 of external memory & lccd seg 9 output 36 34 40 p0.3/ad3/seg10 i/o bit 3 of port 0 & dat a/address bit 3 of external memory & lccd seg 10 output 37 35 41 p0.2/ad2/seg11 i/o bit 2 of port 0 & dat a/address bit 2 of external memory & lccd seg 11 output 38 36 42 p0.1/ad1/seg12 i/o bit 1 of port 0 & dat a/address bit 1 of external memory & lccd seg 12 output 39 37 43 p0.0/ad0/seg13 i/o bit 0 of port 0 & dat a/address bit 0 of external memory & lccd seg 13 output 40 38 44 vdd i drive voltage, vcc 17 23 p4.0 i/o bit 0 of port 4 28 34 p4.1 i/o bit 1 of port 4 39 1 p4.2 i/o bit 2 of port 4 6 12 p4.3 i/o bit 3 of port 4
january 2003 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 5/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary sfr memory map b acc lcdb0 lcdb1 lcdb2 lcdb3 lcdb4 lcdb5 lcdb6 p4 lcdcon psw pwmc0 t2con t2mod rcap2l rcap2h tl2 th2 ip ip1 sconf p3 pwmd0 ie ie1 ifr p2 spwmc spwmd0 scon sbuf p0con p1con p2con p3con wdtc p1 wdtkey tcon tmod tl0 tl1 th0 th1 adscr adcd p0 sp dpl dph (reserved) pcon sfr memory map 0f8h 0f0h 0e8h 0e0h 0d8h 0d0h 0c8h 0c0h 0b8h 0b0h 0a8h 0a0h 98h 90h 88h 80h 0ffh 0f7h 0efh 0e7h 0dfh 0d7h 0cfh 0c7h 0bfh 0b7h 0afh 0a7h 9fh 97h 8fh 87h note: the text of sfrs with bold type characters are extension special function registers for sm79108 addr sfr reset 7 6 5 4 3 2 1 0 8eh adscr 0000_00** com con adcss1 adcss0 ch1 ch0 reserved reserved 8fh adcd 00h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 97h wdtkey 00h wdtkey7 wdtkey6 wdtkey5 wdtke y4 wdtkey3 wdtkey2 wdtkey1 wdtkey0 9ah p0con 00h seg6 seg7 seg8 seg9 seg10 seg11 sge12 seg13 9bh p1con **0*_*0** pwme0 spwme0 9ch p2con 00h seg3 seg2 seg1 seg0 come3 come2 come1 come0 9dh p3con 00h adce3 adce2 adce1 adce0 9fh wdtc 000*_*000 wdte r clear ps2 ps1 ps0 0a3h spwmc0 ****_**00 spfs1 spfs0 0a4h spwmd0 00h spwmd04 spwmd03 spwmd02 spwmd 01 spwmd00 brm02 brm01 brm00 0a9h ie1 ****_0*** eadc 0aah ifr ****_0*** adcif 0b3h pwmd0 00h pwmd07 pwmd06 pwmd05 pwmd04 pwmd03 pwmd02 pwmd01 pwmd00 0b9h ip1 ****_0*** padc 0bfh sconf 0***_***0 wdr reserved alei 0d3h pwmc0 ****_*000 pbs pfs1 pfs0 0d8h p4 ****_1111 p4.3 p4.2 p4.1 p4.1 0dfh lcdcon 000*_*000 lout_en lcd_en seg ls2 ls1 ls0 0e1h lcdb0 00h seg0 seg0 seg0 seg 0 seg1 seg1 seg1 seg1
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 6/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary 1. watch dog timer the watch dog timer (wdt) is a 16-bit free-running counter th at generate reset signal if th e counter overflows. the wdt is useful for systems which are susceptible to noise, power glitches, or electronic s discharge which causing software dead loop or runaway. the wdt function can help user software re cover from abnormal software condition. the wdt is different from timer0, timer1 and timer2 of general 8052. to prevent a wdt reset can be done by software periodically clearing the wdt counter. user shou ld check wdr bit of sconf register whenever unpracticed reset happened the purpose of the secure procedure is to prevent the wdtc value from being changed when system runaway. there is a 250khz rc oscillator embedded in chip. set wdte = ?1? will enable the rc oscillator and the frequency is inde- pendent to the system frequency. to enable the wdt is done by setting 1 to the bit 7 (wdte) of wdtc. after wdte set to 1, the 16-bit counter starts to count with the rc oscillator. it will generate a re set signal when overflows. the wdte bit will be cleared to 0 automatically when sm79108 been reset, either hardware reset or wdt reset. to reset the wdt is done by setting 1 to the clear bit of wdtc before the counter overflow. this will clear the content of the 16-bit counter and let the counter re-start to count from the beginning. 1.1 watch dog timer registers: watch dog key register - (wdtkey, 97h) by default, the wdtc is read only. user need to write values 1eh, 0e1h sequ entially to the wdt key(97h) register to enable the wdtc write attribute, that is mov wdtkey, # 1eh mov wdtkey, # e1h when wdtc is set, user need to write anoth er values e1h, 1eh sequen tially to the wdtkey(97h) register to disable the wdtc write attribute, that is mov wdtkey, # e1h mov wdtkey, # 1eh addr sfr reset 7 6 5 4 3 2 1 0 0e2h lcdb1 00h seg2 seg2 seg2 seg2 seg3 seg3 seg3 seg3 0e3h lcdb2 00h seg4 seg4 seg4 seg4 seg5 seg5 seg5 seg5 0e4h lcdb3 00h seg6 seg6 seg6 seg6 seg7 seg7 seg7 seg7 0e5h lcdb4 00h seg8 seg8 seg8 seg8 seg9 seg9 seg9 seg9 0e6h lcdb5 00h seg10 seg10 seg10 seg10 seg11 seg11 seg11 seg11 0e7h lcdb6 00h seg12 seg12 seg12 seg12 seg13 seg13 seg13 seg13 bit-7 bit-0 wdt key7 wdt key6 wdt key5 wdt key4 wdt key3 wdt key2 wdt key1 wdt key0 read / write: w w w w w w w w reset value: 0 0 0 0 0 0 0 0
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 7/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary watch dog timer registers - wdt control register (wdtc, 9fh) wdte : watch dog timer enable bit clear : watch dog timer reset bit ps[2:0] : overflow period select bits system control register (sconf, 0bfh) wdr : watch dog timer reset. when system reset by watch dog timer overflow, wdr will be set to 1 alei : ale output inhi bit bit, to reduce emi setting bit 0 (alei) of sconf can inhibit the cl ock signal in fosc/6hz output to the ale pin. the bit 7 (wdr) of sconf is watch dog timer reset bit. it will be set to 1 when reset signal generated by wdt overflow. user should check wdr bit whenever unpredicted reset happened. 2. reduce emi function the sm79108 allows user to reduce the em i emission by setting 1 to the bit 0 (ale i) of sconf register . this function will inhibit the clock signal in fosc/6hz output to the ale pin. bit-7 bit-0 wdte r clear unused unused ps2 ps1 ps0 read / write: r/w - r/w - - r/w r/w r/w reset value:000* *000 ps [2:0] overflow period (ms) 000 2.048 001 4.096 010 8.192 011 16.384 100 32.768 101 65.536 110 131.072 111 262.144 bit-7 bit-0 wdr unused unused unused unused reserved unused alei read / write: r/w - - - - - - r/w reset value:0**** * *0
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 8/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary 3. port 4 for plcc or qfp package: the bit addressable port 4 is available with plcc or qfp pack age. the port 4 has only 4 pins and its port address is located at 0d8h. the function of po rt 4 is the same as the function of port 1, port 2 and port 3. port4 (p4, 0d8h) the bit 3, bit 2, bit 1, bit 0 output the setting to pin p4.3, p4.2 , p4.1, p4.0 respectively. 4. spwm function description: the 8-bit spwm channel is composed of an 8-bit register wh ich contains a 5-bit spwm in msb portion and a 3-bit binary rate multiplier (brm) in lsb portion. the value programmed in th e 5-bit spwm portion will dete rmine the pulse length of the output. the 3-bit brm portion will ge nerate and insert certain narrow puls es among an 8-spwm-cycle frame. the number of pulses generated is equal to the number progra mmed in the 3-bit brm portion. the usage of the brm is to generate equivalent 8-bit resolution spwm type dac with reasonably high repetition ra te through 5-bit spwm clock speed. the spfs[1:0] settings of spwmc (0a3h) register are divided of fosc to be spwm clock, fosc/ 2^(spfs[1:0]+1). the spwm output cycl e frame repetition rate (frequency) equals (spwm clock)/32 which is [fosc/ 2^(spfs[1:0]+1)]/32. 4.1 spwm registers - p1con, spwmc0, spwmd0 spwm registers - po rt1 configuration re gister (p1con, 9bh) spwme0 : when the bit set to one, the correspondi ng spwm pin is active as spwm function. when the bit reset to zero, the correspond ing spwm pin is active as i/o pin. four bits are cleared upon reset. pwme0 : when the bit set to one, the corresponding pwm pin is active as pwm function. when the bit reset to zero, the corresponding pwm pin is active as i/o pin. four bits are cleared upon reset. spwm registers - sp wm control regist er (spwmc, 0a3h) bit-7 bit-0 unused unused unused unused p4.3 p4.2 p4.1 p4.0 read / write:----r/wr/wr/wr/w reset value:**** 1111 bit-7 bit-0 unused unused pwme0 unused u nused spwme0 unused unused read / write: - - r/w - - r/w - - reset value: * * 0 * * 0 * * bit-7 bit-0 unused unused unused unused unused unused spfs1 spfs0 read / write:------r/wr/w reset value:******00
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 9/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary spfs[1:0]: these two bits is 2?s power parameter to form a frequency divider for input clock. spwm registers - spwm data register (spwmd0, 0a4h) spwmd0[4:0]: content of spwm data register. it dete rmines duty cycle of spwm output waveform. brm[2:0]: will insert certain narrow pulses among an 8-spwm -cycle frame example of spwm timing diagram: mov spwmd0 , #83h ; spwmd0[4:0]=10h (=16t high, 16t low), brm0[2:0] = 3 mov p1con , #04h ; enable p1.2 as spwm output pin spfs1 spfs0 divider spwm clock, fosc=20mhz spwm clock, fosc=24mhz 0 0 2 10mhz 12mhz 0 1 4 5mhz 6mhz 1 0 8 2.5mhz 3mhz 1 1 16 1.25mhz 1.5mhz bit-7 bit-0 spwmd04 spwmd03 spwmd02 spwmd01 spwmd00 brm02 brm01 brm00 read/write: r/w r/w r/w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0 n = brm[2:0] number of spwm cycles inserted in an 8-cycle frame 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 10/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary if user use fosc=20mhz, spfs[1:0] of spwmc=#03h, then spwm clock = 20mhz/2^4 = 20mhz/16 = 1.25mhz spwm output cycle frame frequency = (20mhz/2^4)/32=39.1khz 5. pwm function description: each pwm channel contains a 8-bit wide pwm data register (p wmdr) to decide number of continuous pulses within a pwm frame cycle. the value pr ogrammed in the register will determine the pulse length of the output. the pwm channel can be configured as 5-bit or 8-bit resolution. if a channel is configured as 5-bit resolution, only lsb 5 bits are available. the value of each pwm data register (pwm dr) is continuously compared with the content of an internal counter to deter- mine the state of each pw m channel output pin. 5.1 pwm registers - pwmc0, pwmd0 pwm registers - pwm contro l register (pwmc0, 0d3h) pfs[1:0]: these two bits is 2?s power parameter to form a frequen cy divider for input clock. pbs: this bit decides channel bit resolution. if pbs is se t, the channel is 5-bit resolution. example : if user use fosc = 20mhz, pfs[1:0] of pwmc = #03h, pbs = 0, then pwm clock = 20mhz / 128 = 156.25khz pwm output cycle frame frequency = 156.25khz / 256 = 610 hz note : for bzzer application bit-7 bit-0 unused unused unused unused unused pbs pfs1 pfs0 read / write: - - - - - r/w r/w r/w reset value: * * * * * 0 0 0 pfs1 pfs0 divider pwm clock, fosc=1 2mhz pwm clock, fosc=24mhz 0 0 16 750khz 1.5mhz 0 1 32 375khz 750khz 1 0 64 187.5khz 375khz 1 1 128 93.75khz 187.5khz 16t 16t 16t 16t 16t 16t 16t 16t 32t 32t 32t 32t 32t 32t 32t 32t 1st cycle frame 2nd cycle frame 3rd cycle frame 4th cycle frame 5th cycle frame 6th cycle frame 7th cycle frame 8th cycle frame 1t 1t 1t spwm clock = 1 / t = fosc / 2^(spfs[1:0]+1) (narrow pulse inserted by brm0[2:0] setting, here brm0[2:0]=3) the spwm output cycle frame frequency = spw m clock / 32 = [fosc/2^(spfs[1:0]+1)]/32
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 11/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary example of pwm timing diagram: for 5-bit resolution channel, m = content of pwmd0: m = 00h m = 01h m = 0fh m = 1fh for 8-bit resolution channel: m = 00h m = 01h m = 7fh m = 0ffh pwm clock = 1/t = fosc / 2^ ( pfs [1:0] + 1 ) 32t 256t pwm registers - pwm data register (pwmd0, 0b3h) pwm[7:0]: content of pwm data register. if pbs is set, only pwm[4:0] are available. bit-7 bit-0 pwmd07 pwmd06 pwmd05 pwmd04 pwmd03 pwmd02 pwmd01 pwmd00 read /write: r/w r/w r/w r/w r/w r/w r/w r/w reset value: 0 0 0 0 0 0 0 0
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 12/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary 6. analog-to-digita l converter (adc) the sm79108 equips with 4-channels, 8-bi t adc which is available at p3.4~p3.7. s/w can select one of the 4 adc chan- nels by setting sfr adc status and control register (adscr , 8eh) bit ch0~ch1. the adc can do single conversion or continuously conversion. when the conversi on is completed, adc puts the result in the adc data register (adcd, 8fh) and sets com bit of adscr (adscr.7). after channel selection bit ch[1:0] of adscr and p3con been set, the selected pin of p3.4~p3.7 will function as adc input pi n instead of general purpose i/o pin which is due to priority of adc function is higher than i/o function. the rest of the p3.4~p3.7 pin will still function as general purpose i/o pin. writes to the port regi ster will have no affect on the port pin that is selected by the adc. read of a port pi n which is in use by the adc will return the value in the port which is been read. 6.1 straight line conversion the adc conversion relationship of input analog signal to digita l output value is a linear straight line conversion relationshi p. it will convert input sig nal in +vdd v or above to 0ffh (full scale) and co nvert input signal +0v or below to 00h. the +vdd is the voltage applied to the ic. 6.2 adc input clock frequency range adc input clock frequency range = 500khz ~ 2.5mhz. user need to be aware of this frequency range limitation when using adc function. the frequency range limitation was induced by th e sample-and-hold and dac converter circuits inside of the adc submodule. if the adc input clock frequency resides outside of the range then adc function may not work. adc input clock frequency = oscillator fr equency / divider. divider elected by adcss[1:0] setting of adscr one conversion time = 20 adc clock cycles / adc input clock frequency maximum sample ra te of adc = adc input clock frequency / 20 6.3 adc register s - adscr, adr adc registers - adscr, 8eh) com: adc conversion complete bit. this bit is a read only bit which is set each time conversion is completed. it is cleared wheneve r adscr is written or adcd is read. reset clears this bit. com = 1 means conversion completed com = 0 means conversion not completed con: adc continuous conversion bit. wh en set, the adc will convert samples continuously and update the adcd register at the end of each conversion. when reset, only one conv ersion is allowed. reset clears this bit. con = 1 means continuous mode con = 0 means signal mode bit-7 bit-0 com con adcss1 adcss0 ch1 ch0 r r read /write: r r/w r/w r/w r/w r/w - - reset value: 0 0 0 0 0 0 * *
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 13/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary adcss[1:0]: adcss channel select bit. ch[1:0] : adc channel select bit. thes e bits are used to select one of the adc channels. note: adc_clk frequency range 500khz ~ 2.5mhz adc registers - adc data register (adcd, 8fh) adc puts the result in the adc data regi ster (adcd, 8fh) after each conversion. the adcd register is read only regis- ter. the content of the a dcd will be 00h after reset. ex : osc = 20mhz adcss[1:0] = 00 adc input clock = 20/8 = 2.5mhz (max) one conversion time = 20 / 2.5mhz = 8us adc max sample reta = 2.5mhz / 20 = 125khz port 3 configuration register (p3con, 9dh) set adce3 = 1 enables the adc function on pin p3.7/a15/adc3, adce3 = 0 disables the adc function on pin p3.7/a15/adc3, set adce2 = 1 enables the adc function on pin p3.6/a14/adc2, adce2 = 0 disables the adc function on pin p3.6/a14/adc2, adcss1 adcss0 adc_clk 0 0 fosc / 8 (below 20mhz) 0 1 fosc / 16 1 0 fosc / 32 1 1 fosc / 64 ch1 ch0 input select 0 0 ch0 0 1 ch1 1 0 ch2 1 1 ch3 bit-7 bit-0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 read /write:rrrrrrrr reset value:00000000 bit-7 bit-0 adce3 adce2 adce1 adce0 unuse d unused unused unused read /write: r/w r/w r/w r/w - - - - reset value: 0 0 0 0 * * * *
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 14/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary set adce1 = 1 enables the adc function on pin p3.5/a13/adc1, adce1 = 0 disables the adc function on pin p3.5/a13/adc1, set adce0 = 1 enables the adc function on pin p3.4/a12/adc0, adce0 = 0 disables the adc function on pin p3.4/a12/adc0, user may compare bits adce[3:0] of p3co n with bits ch[1:0] of adscr. user ma y consider p3con as register for dis- tinguish general purpose i/o function from other specific func tions. after bit adce[3:0] been set, the corresponding i/o pin will be assigned as high impeda nce input pins for signal inpu t. on the other hand, the sett ing of ch[1:0] will select adc channels accordingly. 6.4 adc interrupt the adc module will gene rate one interrupt once one analog-to-digital conversion is completed. the ad c interrupt vector locates at 4bh. there are three sfrs for configuring adc inte rrupt: ip1, ie1 and ifr. to use adc interrupt is the same as to use other generic 8052 interrupts. that means using ea dc of ie1 for enable/disable adc interrupt, using padc for assign adc interrupt prio rity. whenever adc interrupt occurs, adcif will be set to 1. after adc inte rrupt subroutine (vec- tor) been executed, adcif will be cleared to 0. i nterrupt priority i register (ip1, 0b9h ) interrupt priority bit padc = 1 assigns hi gh interrupt priority of adc interrupt interrupt priority bit padc = 0 assigns lo w interrupt priority of adc interrupt interrupt enable i re gister (ie1, 0a9h) interrupt enable bi t eadc = 1 enables the adc interrupt interrupt priority bi t eadc = 0 disables the adc interrupt interrupt flag regi ster (ifr, 0aah) interrupt flag bit adcif will be set to 1 when adc in terrupt occurs. interrup t flag bit adcif will be clear to 0 if adc interrupt subroutine executed. bit-7 bit-0 unused unused unused unused padc unused unused unused read /write: - - - - r/w - - - reset value:****0*** bit-7 bit-0 unused unused unused unused eadc unused unused unused read /write: - - - - r/w - - - reset value:****0*** bit-7 bit-0 unused unused unused unused adcif unused unused unused read /write: - - - - r/w - - - reset value:****0***
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 15/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary 7. lcd driver sm79108 incorporates an on-chip lcd driver which generates segment and common signals output according to the dis- play data saved in lcd buffer registers (0e1h~0e7h) and incorporates segment and common drivers which can drive the lcd panel directly. the on chip lcd driver has the following features: 1/4 duty (time multip lexing by 4) and 1/3 bias lcd segment driver 0.88 ma operation current (1.2 ua in power down mode) 56 bits of display data buffer 14 segment driver an d 4 common driver outputs a fram es frequency ca n be selected 7.1 lcd control register (lcdcon, 0dfh) lcdcon7~lcdcon0: lcd control register is used to control lcd driver operation lcd_on: lcd display bit = 1:lcd display on = 0:lcd display off lcd_en: lcd enable bit seg: = 1:enables the lcd function on pi n #psen/seg4 and ale/seg5 = 0:no operation ls[2:0]: frequen cy prescaler select, determine the clock frequency of lcd driver, fclk_lcd bit-7 bit-0 lcd_on lcd_en seg unused unused ls2 ls1 ls0 read /write: r/w r/w r/w - - r/w r/w r/w reset value: 0 0 0 * * 0 0 0 ls2 ls1 ls0 prescaler select 000 1 001 2 10 4 011 8 100 16 101 32 110 64 111 128
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 16/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary the clock frequency of lcd driver is obtained using the following formula: fclk_lcd = { [fosc / 2 ] / 32 x prescaler } the frame of lcd driver is de termined as follows: frame = fclk_lcd / 256 the typical range of fframe is: 1026hz ~ 8hz at 16mhz (fosc = 8mhz) 7.2 lcd buffer registers (l cdb0 ~ lcdb6, 0e1h ~ 0e7h) addressing map of the lcd buffer re gisters is shown as following: 7.3 timing chart of lcd driver output the 14 segment drivers and the 4 comm on drivers are 4-level outputs that switch between vcc and the v1, v2 and vss lcd driver voltages levels. the output states are determin ed by the display data values which st ored in the lcd buffer registers (0e1h ~0e7h). the lcd driver's outputs are used to dr ive a 1/3-bias, 1/4-duty lcd panel. 7.4 the output control of segments and commons port 2 configuration regist er (p2con) control com0 ~ com3 and seg 0 ~ seg3 output; port 0 configuration register (p0con) controls seg6 ~ seg13 outputs. the bit 5 of lcd control r egister control the seg4 and seg5 outputs. com3 com2 com1 com0 com3 com2 com1 com0 mnemonic address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lcdb0 e1h seg0 seg0 seg0 seg0 seg1 seg1 seg1 seg1 lcdb1 e2h seg2 seg2 seg2 seg2 seg3 seg3 seg3 seg3 lcdb2 e3h seg4 seg4 seg4 seg4 seg5 seg5 seg5 seg5 lcdb3 e4h seg6 seg6 seg6 seg6 seg7 seg7 seg7 seg7 lcdb4 e5h seg8 seg8 seg8 seg8 seg9 seg9 seg9 seg9 lcdb5 e6h seg10 seg10 seg10 seg10 seg11 seg11 seg11 seg11 lcdb6 e7h seg12 seg12 seg12 seg12 seg13 seg13 seg13 seg13
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 17/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary vcc v1 com0 v2 vss com0 com1 com2 com3 0 0 0 0 all segments are off 1 0 0 0 segments connected to com0 are on 0 1 0 0 segments connected to com1 are on 1 1 1 1 all segments are on frame period figure 6.1 output st ates determination vcc v1 com1 v2 vss vcc v1 com2 v2 vss vcc v1 com3 v2 vss vcc v1 seg0 v2 vss vcc v1 seg1 v2 vss vcc v1 seg2 v2 vss vcc v1 seg3 v2 vss
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 18/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary operating conditions dc characteristics (ta = -40 o c to 85 o c , vcc = 5v) symbol description min. typ. max. unit. remarks ta operating temperature -40 25 85 o c ambient temperature under bias ts storage temperature -55 25 155 o c vcc5 supply voltage 4.5 5.0 5.5 v vcc3 supply voltage 3 3.3 3.6 v fosc 25 oscillator frequency 3.0 25 25 mhz for 5v, 3.3v application fosc 40 oscillator frequency 3.0 40 40 mhz for 5v application symbol parameter valid min. max. unit test conditions vil1 input low voltage port 0,1,2,3,4,#ea -0.5 1.0 v vcc = 5v vil2 input low voltage res, xtal1 0 0.8 v ? vih1 input high voltage port 0,1,2,3,4,#ea 2.0 vcc+0.5 v ? vih2 input high voltage res, xtal1 70%vcc vcc+0.5 v ? vol1 output low volta ge port 12,3,4 0.4 v iol = 1.6ma vol2 output low voltage port 0,2,port 3.0~port 3.3, ale, #psen 0.4 v iol = 3.2ma voh1 output high voltage port 1, 2, 3, ale, #psen 2.4 v ioh = -60ua 90%vcc v ioh = -10ua voh2 output high voltage port 0 2.4 v ioh = -800ua 90%vcc v ioh = -80ua iil logical 0 input current port 1,2,4, port 3.0~port 3.3 -50 ua vin = 0.45v itl logical transition current port 1,2,4, port 3.0~ port3.3 -650 ua vin = 2.0v ili input leakage current port 0, #ea 10 ua vin = 0.45v 10 ua vin = 5v r rst reset pulldown resistor 18 90 kohm c io pin capacitance 10 pf freq=1mhz, ta=25 o c i cc power supply current vdd 20 ma active mode, 16mhz 10 ma idle mode, 16mhz 100 ua down mode, 16mhz note1: under steady stat e (non-transient) conditions, iol must be externally limited as follows: maximum iol per port pin : 10ma maximum iol per 8-bit port : port 0 :26ma port 1,2,3 :15ma maximum total iol for all output pins : 71ma if iol exceeds the condition, vol may exceed the related specificat ion. pins are not guaranteed to sink current greater than t he listed test conditions. note2 : minimum vcc for power-down is 2v.
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 19/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary symbol parameter valid cycle fosc=16mhz min. typ. max variable fosc min. typ. max unit remarks t lhll ale pulse width rd/wrt 115 2xt - 10 ns t avll address valid to ale low rd/wrt 43 t - 20 ns t llax address hold after ale low rd/wrt 53 t - 10 ns t lliv ale low to valid instruction in rd 240 4xt - 10 ns t llpl ale low to #psen low rd 53 t - 10 ns t plph #psen pulse width rd 173 3xt - 15 ns t pliv #psen low to valid instruction in rd 177 3xt - 10 ns t pxix instruction hold af ter #psen rd 0 0 ns t pxiz instruction float af ter #psen rd 87 t + 25 ns t aviv address to valid instruction in rd 292 5xt - 20 ns t plaz #psen low to address float rd 10 10 ns t rlrh #rd pulse width rd 365 6xt - 10 ns t wlwh #wr pulse width wrt 365 6xt - 10 ns t rldv #rd low to valid data in rd 302 5xt - 10 ns t rhdx data hold after #rd rd 0 0 ns t rhdz data float after #rd rd 145 2xt + 20 ns t lldv ale low to valid data in rd 590 8xt - 10 ns t avdv address to valid data in rd 542 9xt - 20 ns t llyl ale low to #wr high or #rd low rd/wrt 178 197 3xt - 10 3xt + 10 ns t avyl address valid to #wr or #rd low rd/wrt 230 4xt - 20 ns t qvwh data valid to #wr high wrt 403 7xt - 35 ns t qvwx data valid to #wr transition wrt 38 t - 25 ns t whqx data hold after #wr wrt 73 t + 10 ns t rlaz #rd low to address float rd 5 ns t yalh #wr or #rd high to ale high rd/wrt 53 72 t -10 t + 10 ns t chcl clock fall time ns t clcx clock low time ns t clch clock rise time ns t chcx clock high time ns t, tclcl clock period 63 1/fosc ns ac characteristics (16/25/40mhz, operating conditions; cl for port 0, ale and psen outputs=150pf; cl for all other output=80pf) vcc vcc rst xtal2 xtal1 vss vcc po ea (nc) clock signal icc active mode test circuit 8 icc sm79108
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 20/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary timing critical, requirement of external clock (vss=0.0v is assumed) vdd-0.5v 0.45v 70%vdd 20%vdd-0.1v tchcl tclcl tchcx tclch tclcx tm.i external program memory read cycle tm.ii external data memory read cycle #psen ale port 0 port 2 tplph tlhll tllpl tavll tllax tpxix tpxiz taviv tplaz tpliv a0 - a7 instruction. in a0 - a7 a8 - a15 a8 - a15 #psen ale #rd port 0 port 2 tyhlh tlldv tllyl trlrh tavll tllax trlaz tavyl tavdv p2.0 - p2.7 or a8 - a15 from dph trhdz trhdx a0 - a7 from ri or dpl data in a0 - a7 from pcl instrl in a8 - a15 from pch trldv
january 2003 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 21/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary tm.iii external da ta memory write cycle #psen ale #wr port 0 port 2 tlhll tyhlh tavll tllax tqvwx tllyl tavyl twlwh twhqx tqvwh a0-a7 from pcl instrl in p2.0-p2.7 or a8-a15 from dph a8-a15 from pch a0-a7 from ri or dpl data out note: oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. user should check with the crystal or ceramic resonator manufacturer for appropriate value of external components. xi x2 sm79108 x'tal r c1 c2 application reference valid for sm79108 x?tal 3mhz 6mhz 12mhz 16mhz c1 30pf 30pf 30pf 30pf c2 30pf 30pf 30pf 30pf r open open open open x?tal 20mhz 25mhz 33mhz 40mhz c1 22pf 15pf 5pf 2pf c2 22pf 15pf 5pf 2pf r open 62k ? 6.8k ? 4.7k ?
january 2003 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 22/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary 40l 600mil pdip information a1 e1 b1 b l a a2 d s ea c a e1 e note: 1. dimension d max & include mold flash or tie bar 2. dimension e1 does not include inter lead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 4. dimension b1 does not include dambar protrusion/ 5. controlling dimension is inch. 6. general appearance spec. should base on final visual symbol dimension in inch minimal/maximal dimension in mm minimal/maximal a - / 0.210 - / 5.33 a1 0.010 / - 0.25 / - a2 0.150 / 0.160 3.81 / 4.06 b 0.016 / 0.022 0.41 / 0.56 b1 0.048 / 0.054 1.22 / 1.37 c 0.008 / 0.014 0.20 / 0.36 d - / 2.070 - / 52.58 e 0.590 / 0.610 14.99 / 15.49 e1 0.540 / 0.552 13.72 / 14.02 e1 0.090 / 0.110 2.29 / 2.79 l 0.120 / 0.140 3.05 / 3.56 a 0 / 15 0 / 15 ea 0.630 / 0.670 16.00 / 17.02 s - / 0.090 - / 2.29 burrs. intrusion. inspection spec.
january 2003 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 23/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary symbol dimension in inch minimal/maximal dimension in mm minimal/maximal a - / 0.185 - / 4.70 a1 0.020 / - 0.51 / - a2 0.145 / 0.155 3.68 / 3.94 b1 0.026 / 0.032 0.66 / 0.81 b 0.016 / 0.022 0.41 / 0.56 c 0.008 / 0.014 0.20 / 0.36 d 0.648 / 0.658 16.46 / 16.71 e 0.648 / 0.658 16.46 / 16.71 e 0.050 bsc 1.27 bsc gd 0.590 / 0.630 14.99 / 16.00 ge 0.590 / 0.630 14.99 / 16.00 hd 0.680 / 0.700 17.27 / 17.78 he 0.680 / 0.700 17.27 / 17.78 l 0.090 / 0.110 2.29 / 2.79 - / 0.004 - / 0.10 / / 44l plastic chip carrier (plcc) ehe d hd 6 7 note: 1. dimension d & e does not include inter lead flash. 2. dimension b1 does not include dambar protrusion/ intrusion. 3. controlling dimension: inch 4. general appearance spec. should base on final visual inspection spec. y l y ge a2 a a1 e b1 b c gd
january 2003 specifications subject to change with out notice,contact your sales representatives for the most recent information. 24/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary 44l plastic quad flat package e2 e1 e d2 d1 d e1 e seating plane l1 l c s e b a2 a1 a 2 3 r1 r2 gage plane 0.25 mm note: dimension d1 and e1 do not include mold protrusion. allowance protrusion is 0.25mm per side. dimension d1 and e1 do include mold mismatch and are determined datum plane. dimension b does not include dumber protrusion. allowance dumber protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dumber cannot be located on the lower radius or the lead foot. symbol dimension in inch minimal/maximal dimension in mm minimal/maximal a - / 0.100 - / 2.55 a1 0.006 / 0.014 0.15 / 0.35 a2 0.071 / 0.087 1.80 / 2.20 b 0.012 / 0.018 0.30 / 0.45 c 0.004 / 0.009 0.09 / 0.20 d 0.520 bsc 13.20 bsc d1 0.394 bsc 10.00 bsc d2 0.315 8.00 e 0.520 bsc 13.20 bsc e1 0.394 bsc 10.00 bsc e2 0.315 8.00 e 0.031 bsc 0.80 bsc l 0.029 / 0.041 0.73 / 1.03 l1 0.063 1.60 r1 0.005 / - 0.13 / - r2 0.005 / 0.012 0.13 / 0.30 s 0.008 / - 0.20 / - 0 / 7 as left 1 0 / - as left 2 10 ref as left 3 7 ref as left c 0.004 0.10 c
january 2003 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 25/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary company contact info programmer model number advantech 7f, no.98, ming-chung rd., shin-tien city, taipei, taiwan, roc web site: http://www.aec.com.tw tel:02-22182325 fax:02-22182435 e-mail: aecwebmaster@advantech.com.tw labtool - 48 (1 * 1) labtool - 848 (1*8) * note: not yet, about 3/e?03 hi-lo 4f, no. 20, 22, ln, 76, rui guang rd., nei hu, taipei, taiwan, roc. web site: http://www.h ilosystems.com.tw tel:02-87923301 fax:02-87923285 e-mail: support@hilosystems.com.tw all - 11 (1*1) gang - 08 (1*8) * note: not yet, about 3/e?03 leap 6th f1-4, lane 609, chunghsin rd., sec. 5, sanchung, taipei hsien, taiwan, roc web site: http://www.leap.com.tw tel:02-29991860 fax:02-29990015 e-mail: service@leap.com.tw su - 2000 (1*8) * note: not yet, about 3/e?03 xeltek electronic co., ltd 338 hongwu road, nanjing, china 210002 web site: http://www.xeltek-cn.com tel:+86-25-4408399, 4543153-206 e-mail: xelclw@jlonline.com, xelgbw@jlonline.com superpro/2000 (1*1) superpro/680 (1*1) superpro/280 (1*1) superpro/l+(1*1) * note: not yet, about 3/e?03 emcu writer list
january 2003 specifications subject to change without notice,contact yo ur sales representatives for the most recent information. 26/26 preliminary ver 1.0 sm79108 01/03 syncmos technologies inc. sm79108 preliminary company : dept, section : position title : inquiry date : ref no : feedback / inquiry: :syncmos technologies, inc. :mkt / customer service dept. :886-3-579-2960 :886-3-578-0493 :886-3-579-2987 :886-3-578-3344 # 2667 to attn fax te l from : description:

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